√完了しました！ verilog ifdef else 825270-Verilog ifdef or condition

' 'timescale timescale ? · Verilog `ifdef equivalent in VHDL Hi I've just learned that in Verilog you can use an `ifdef statement that makes Quartus ignore the following code (until the next`endif) you can define a macro in the qsf file (or through the GUI) to decide which parts of code to ignore is there an equivalent in VHDL?The #ifdef, #ifndef, #elseif, #elif, #else, and